Data processing systems typically experience data bottlenecks under older input/output (I/O) standard architectures such as the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA). These bottlenecks arise when data transfers are unable to keep pace with the requirements of a processing unit or other component within the data processing system. Alternative I/O architectures have been developed to eliminate such bottleneck by providing higher bandwidth buses. One such alternative is the peripheral component interconnect (PCI) local bus, a high performance 32-bit or 64-bit bus with multiplexed address and data lines. The mechanical, electrical, and operation characteristics for the current PCI local bus standard may be found in PCI Local Bus Specification, Revision 2.1 ("the current PCI specification"), available from the PCI Special Interest Group in Portland, Oreg. The current PCI specification and/or variants are expected to be employed in data processing systems for a considerable time into the future.
The PCI local bus specification provides a processor-independent interface to add-in boards, also commonly referred to as expansion cards or adapters. Because of AC switching characteristic limitations, a PCI bus is typically limited in both data transfer rate and fan-out (number of adapter slots supported). Data transfer rate and fan-out in a PCI bus are interdependent, such that achieving an increase in one generally results in a decrease in the other. The current 33 MHz 64-bit PCI architecture definition provides a peak data transfer rate of 264 MB/s and supports up to 4 slots per PCI I/O bus. This data rate is slow for many high performance adapters under contemporary workstation requirements. The current 66 MHz PCI architecture definition provides a peak data transfer rate of 528 MB/s, but only supports up to 2 slots per PCI I/O bus. This fan-out is extremely restrictive, limiting the usefulness of 66 MHz PCI architecture.
A high performance, general purpose parallel I/O bus similar to PCI, but with better performance and fan-out than provided by the current 66 MHz PCI definition, may be provided. The enhanced bus architecture builds upon the current 66 MHz PCI architecture but is not directly backwards-compatible with the existing PCI bus architecture specification since the connectors employed for the existing PCI bus architectures cannot be employed for the enhanced bus architecture. It would be desirable, therefore, to provide circuitry supporting the enhanced bus architecture.